module project2_register(iClk, RegWrite, writeregister, writeaddress, readaddress1, readaddress2, readregister1, readregister2);

input [7:0] writeregister;
input [4:0] writeaddress;
input [4:0] readaddress1, readaddress2;
input iClk;
output [7:0] readregister1, readregister2;

reg [7:0]register[31:0];

initial begin
register[7:0][31:0]=0;

always @(posedge iClk) begin
if(RegWrite)
register[writeaddress]<=writeregister;
end

assign readregister1[7:0] = (readaddress1 !=0) ? register[7:0] : 0;
assign readregister2[7:0] = (readaddress2 !=0) ? register[7:0] : 0;

endmodule